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<identifier identifierType="Handle">21.15106/11b2593a-f022-11df-9c01-001eece77216</identifier>
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<creators>
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<creator>
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<creatorName>Sazeides, Yanos</creatorName>
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<givenName>Yanos</givenName>
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<familyName>Sazeides</familyName>
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<affiliation>University of Cyprus</affiliation>
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</creator>
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<creator>
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<creatorName>Liqiang, He</creatorName>
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<givenName>He</givenName>
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<familyName>Liqiang</familyName>
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<affiliation>University of Cyprus</affiliation>
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</creator>
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</creators>
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<contributorName>DNet Team</contributorName>
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<titles>
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<title>SA-multicore</title>
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</titles>
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<publisher>EGI Applications Database</publisher>
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<subject>Applications</subject>
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<alternateIdentifier alternateIdentifierType="URL" xmlns="http://datacite.org/schema/kernel-4">https://appdb.egi.eu/store/software/sa.multicore</alternateIdentifier>
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<formats>
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<format>Python</format>
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<version>3.1</version>
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<rightsList>
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</rightsList>
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<descriptions>
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<description descriptionType="Abstract">Sim-alpha-multicore, a simulator which makes a detailed timing simulation for a multicore microprocessor. The sim-alpha-multicore is an extension version of sim-alpha microarchitecture simulator. Sim-alpha is a widely used single core processor simulator in the academic community. Our simulator extends the single core simulator to multicore simulator using the standand pthread library.</description>
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<description descriptionType="TechnicalInfo">Taverna Workbench</description>
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<description descriptionType="DistributionForm">sourceCode</description>
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